Non-volatile memory cells using floating gate for storage are well known in the art. Typically, these types of memory cells use a conductive floating gate to store one or more bits, i.e. either the floating gate stores some charges or it does not. The charges stored on a floating gate control the conduction of charges in a channel of a transistor, with the transistor having a “control gate”, “source” and a “drain,” with the “source” and “drain” in a substrate and a channel region therebetween. Clearly the terms “source” and “drain” may be interchanged. The floating gate controls the conduction of current either in the entire channel region or in a portion thereof. Typically, “programming” is the act of adding electrons to the floating gate, thereby lowering the memory cell read current. Although there are various mechanism to program a floating gate non-volatile memory cell, the present invention is an algorithm to improve the speed of programming of a floating gate non-volatile memory cell which occurs by either the mechanism of hot electron injection from the channel region or by source side injection of electrons from the channel region. During programming, a “high” voltage is applied to one of the terminals of the transistor—hereinafter called the high voltage terminal. Intuitively, one expects programming to be more efficient, i.e. the memory cell read current after programming decreases as the programming voltage is increased. This is termed program acceleration. However, it has been found that at a certain point of the programming voltage, any further increase of the programming voltage would actually cause the memory cell read current after programming to increase. This is termed program deceleration. Between the range at which program acceleration levels off, and when program deceleration starts is a window of ideal programming voltages. This is termed Program Acceleration Deceleration (PAD) Window. As the scale of integration increases, i.e. the geometry for semiconductor processing decreases, the PAD Window narrows. Further, the PAD Window also narrows as temperature increases.
Referring to FIG. 1, it can be seen that for one example of a floating gate non-volatile memory cell, at a certain geometry size, the program acceleration at 20° C. ranges from below 6.5 volts to approximately 7.0 volts. The program deceleration ranges from approximately 8.4 volts and up. Thus the PAD Window is approximately from about 7.0 volts to about 8.4 volts. However, for the same non-volatile memory cell at 100° C., the PAD Window disappears and it narrows at approximately 8.25 volts. This limitation on the range for the PAD Window places a constraint on the accuracy of other electronic circuit components in a non-volatile memory device, such as charge pump and the like.
There are generally two types of non-volatile memory cells: stacked gate or split gate. In a stacked gate floating gate non-volatile memory cell, the floating gate is positioned adjacent to the entire channel region and controls the flow of current in the entire channel region. The control gate is capacitively coupled to the floating gate. In a split gate floating gate non-volatile memory cell, the floating gate is positioned adjacent to a first portion of the channel region and controls the flow of current in that first portion. A control gate is positioned laterally spaced apart from the floating gate and controls a second portion of the channel region. See U.S. Pat. No. 5,029,130 for an example of a split gate floating gate non-volatile memory cell, and array, whose disclosure is incorporated herein by reference in its entirety. The present invention can be used in stacked gate or split gate types of floating gate non-volatile memory cells.